In existing sub-20 nm technology, three-dimensional multi-gate devices such as FinFETs or tri-gate devices are predominant designs. Such designs can increase gate control capability and suppress leakage and Short Channel Effects (SCEs).
For example, double-gate SOI-based MOSFETs can suppress the SCEs and Drain Induced Barrier Lowering (DIBL) effects more effectively, have lower junction capacitances, and achieve lower channel doping, as compared with conventional single-gate bulk-Si-based or SOI-based MOSFETs. A substantially 2 times greater drive current can be achieved by appropriately setting a work function of a metal gate, resulting in a lower Equivalent Oxide Thickness (EOT) requirement. Further, a tri-gate device has a gate surrounding a top surface and opposite side surfaces of a channel region, and thus has more powerful gate control capability than the double-gate devices. Furthermore, all-around nanowire multi-gate devices are more advantageous.
Gate-all-around nanowire devices have better gate control capability, can suppress the SCEs more effectively, and thus are more advantageous in the scaling of sub-14 nm technology. However, such devices have problems such as tiny conductive channels, and thus cannot provide more drive currents in an effective silicon planar area.
For example, for a gate-all-around nanowire device with an effective line width of 1 μm, the device should has a dimension satisfying d*n+(n−1)*s=1 μm and π*d*n>1 μm, where d indicates a diameter of a single nanowire (NW), n indicates a number of NWs, and s indicates a pitch between the NWs. Therefore, in cases where the diameter d is 3 nm, 5 nm, 7 nm, and 10 nm, respectively, the pitch s between the NWs should be smaller than 6.4 nm, 10.6 nm, 15 nm, and 21.4 nm, respectively. As a result, to be comparable to a bulk-Si based device with a gate width of 1 μm, the NW device should have its NWs arranged in parallel very closely. According to existing exposure and etching techniques for FinFETs (with an interval between fins of about 60 nm), it is very difficult to achieve such a vertical arrangement of NWs with an extremely small pitch.
It is an effective way to increase the drive current by vertically stacking gate-all-around NWs. However, it is difficult to achieve or manufacture in practice. It is a challenging task to make it compatible with the conventional processes at low cost. For example, a conventional method of making stacked NWs comprises heteroepitaxy of Si/SiGe layers and selective etching. Specifically, a stack of alternating Si and SiGe layers may be formed on a Buried Oxide (BOX) by heteroepitaxy, and then the SiGe layers may be selectively removed by, for example, wet etching, to leave a stack of Si NWs. This method is seriously limited by the quality of the epitaxial layers, and incurs great cost. On the other hand, a conventional NW stack (where a gate fills in gaps between NWs, that is, each of the NWs is surrounded by a gate stack of HK/MG) has a relatively small total effective current per unit footprint, while a fin without stacked NWs has a greater effective conductive section (taken in a direction perpendicular to an extending direction of the fin, i.e., perpendicular to a channel) at the same footprint.
Therefore, there is a need for a novel NW device and a method of manufacturing the same, to, for example, increase an effective width of a conductive channel and thus improve a drive current.